(1) Field of the Invention
The present invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of improving the gap filling characteristics of an intermetal dielectric layer for sub-half-micron semiconductor devices in the fabrication of integrated circuits.
(2) Description of the Prior Art
In the fabrication of integrated circuit devices, semiconductor device structures such as gate electrodes and source and drain regions are typically formed in and on a semiconductor substrate. An insulating layer is deposited over the surface of the substrate and planarized. Next, a first metal conducting layer is deposited and patterned to form metal lines. An intermetal dielectric layer is deposited overlying the metal lines. A second metal layer will then be deposited and patterned. Further layers of metallization may be formed. As the size of semiconductor devices decreases to the sub-half-micron regime, the size of the gap between the patterned metal areas decreases. This leads to stringent requirements for the manufacturing of intermetal dielectrics, including: 1) voidless filling of narrow gaps between metal conductors, 2) a planar surface for successful patterning and etching of the next blanket metal deposition, and 3) freedom from spin-on-glass poison via problems.
Many workers in the field have attempted to meet these difficult intermetal dielectric requirements. Many of the previous inventions make use of O.sub.3 -TEOS (ozone-tetraethoxysilane) or HDP-CVD (high density plasma chemical vapor deposition) silicon oxide. These techniques have problems of either low throughput or the need of chemical mechanical polishing (CMP) for surface planarity. For example, U.S. Pat. No. 5,393,708 to Hsia et al uses O.sub.3 -TEOS to fill trenches in the layer structure and etches back the O.sub.3 -TEOS to leave it only within the trenches. U.S. Pat. No. 5,354,715 to Wang et al teaches O.sub.3 -TEOS as a gap-filling material and in-situ etchback for planarization. U.S. Pat. No. 5,426,076 to Moghadam teaches deposition of a second layer of silicon oxide to fill gaps and then etchback of the silicon oxide to remove it from all regions except within the gaps. U.S. Pat. No. 5,459,105 to Matsuura teaches a planarization method where multiple oxide layers are formed over a metal pattern and then etched back. U.S. Pat. No. 5,270,264 to Andideh et al teaches gap filling including a noble gas sputter etching and redeposition of the etched material in the gaps.
Other methods use a fluorine-doped gap-filling layer. U.S. Pat. No. 5,429,995 to Nishiyama et al teach gap filling using a film formed by source gases containing silicon, oxygen, and fluorine. U.S. Pat. No. 5,334,552 to Homma teaches depositing a fluorine-containing silicon oxide film followed by a resist or spin-on-glass film and etching back both films. The paper, "High-Quality and Low Dielectric Constant SiO2 CVD Using High Density Plasma" by N. Hayasaka et al, 1993 Dry Process Symposium, discusses forming a high quality fluorine-doped silicon oxide film. U.S. Pat. No. 5,275,977 to Otsubo et al teaches the use of a fluorine compound in the deposition of a silicon oxide film and simultaneous etching of the film. U.S. Pat. No. 5,294,294 to Namose teaches an oxide etching method using a fluorine gas and an inert gas.